Saturday, August 1, 2020

DIGITAL LOGIC AND COMPUTER DESIGN - 2017 | B.SC CS 1ST YEAR | MJPRU | EXAM PAPER | My CS Tutorial

My CS Tutorial August 01, 2020

Digital logic and computer design exam paper | My CS Tutorial

Paper Code: 13505
1505
B.Sc. (Computer Science) (Part 1)
Examination, 2017
Paper No. 2.2
DIGITAL LOGIC AND COMPUTER DESIGN

Time: Three Hours][Maximum Marks: 33

Note: Attempt five questions in all. Select one question from each Section.

Section-A

1. (a) Explain the principle of duality in Boolean algebra.4

(b) Explain what do you understand by don’t conditions.3

2. (a) How are the squares of a K-map labelled ? Explain with examples.4

(b) Simplify the expression by K-map method :3

$\bar{A}B\bar{C}+AB\bar{C}+A\bar{B}\bar{C}$

Section-B

3. (a) “AND, OR and NOT gates are logically complete.” Discuss.4

(b) Construct logic circuit diagram for a half adder using only NAND gates.3

4. (a) Draw K-map and simplify the following funcions :

$Y(A,B,C,D)=\sum (0,2,4,6,8,10,12,14,15)$ 4

(b) Explain the following :

(i) Combinational logic

(ii) Truth table3

Section-C

5. (a) What are modulus of a counter ? Discuss the working principle of mod-3 counter.4

(b) Explain the terms “UP COunter” and “Down Counter.”3

6. (a) What are the shortcomings of an S-R flip-flop ?How is this shortcoming removed ?3

(b) Explain the following :4

(i) Tiggers

(ii) State reduction

Section-D

7. (a) Discuss the function of encoders, decoders and code converters.4

(b) Differentiate between n-bit register and a n-bit latch.3

8. (a) What are buffers/derivers ? Explain.3

(b) Explain the following :4

(i) Synchronous counter

(ii) Timing sequences

Section-E

9. (a) Explain inter register transfer. $2\tfrac{1}{2}$

(b) Explain decimal, floating and non-numeric data. $2\tfrac{1}{2}$

10. Explain any two of the following : $2\tfrac{1}{2}$ each

(i) Overflow

(ii) MOD-12 counters

(iii) Shift counter

(iv) Multiplexers/Selectors

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